1. Field of the Invention
The present invention relates to a multiprocessor system utilizing dual-port random access memories (referred to as "DPMs", hereinafter) each used as a memory circuit (referred to as a "shared memory" hereinafter) shared by a host central processing unit (host-CPU) circuit and one of the sub-central processing unit (sub-CPU) circuits and, particularly, to a method of detecting abnormal operation of any of the sub-CPU circuits and resetting the sub-CPU circuit operating abnormally.
2. Description of the Prior Art
A conventional multiprocessor system of this kind includes a host-CPU circuit, a plurality of sub-CPU circuits and shared memories corresponding in number to the sub-CPU circuits. Each of the host-CPU circuit and the sub-CPU circuits includes a CPU for processing data, etc., a read-only memory (ROM) circuit for storing programs, etc., of the CPU circuit, a random access memory (RAM) circuit used for arithmetic operations, an input-output (I/O) circuit which is an interface circuit between the CPU and external devices, and a watch-dog timer circuit (U.S. Pat. No. 4,752,930) for monitoring operations of the CPU. The host-CPU circuit and each sub-CPU circuit share a DPM as a shared memory for data, etc. In such multiprocessor systems, the sub CPU circuits collect data, such as alarm information of devices and performance information in the DMPs associated therewith, and the host-CPU circuit processes the data stored in the DPMs.
The host- and sub-CPU circuits are continuously monitored by the internally provided watch-dog timers, respectively, and, when any CPU circuit operates abnormally, for example, it runs abnormally, the CPU circuit is reset by the associated watch-dog timer. Since, however, the DPM connected thereto may have been written with abnormal data before such resetting of the CPU, or normal data is lost by the resetting operation, the reliability of data in the DPM is lost as a whole. Further, it is inevitable that any CPU which operates abnormally may read in data written from a CPU operating normally as different data and/or read in data from an erroneous address. That is, when any of CPUs of the multiprocessor system becomes abnormal, data commonly stored in the DPM associated therewith becomes meaningless.
Further, the host-CPU circuit or the sub-CPU circuit cannot know when the sub-CPU circuit or the host-CPU circuit becomes abnormal and therefore there is a problem of data inconsistently occurred in exchange of data between them. For example, the host-CPU cannot detect the loss of data in the DPM due to resetting of an associated sub-CPU. Therefore, the host-CPU circuit may process data a portion of which is lost as if it is correct data. When such erroneous data thus processed as correct data is used by another sub-CPU circuit through the host-CPU circuit, the influence of data loss may be spread over the whole processor system.
Further, in the multiprocessor system, since each CPU requires a watch-dog timer, it becomes expensive.